1. Field of the Invention
The present invention relates to a wiring forming system and wiring forming method for forming wiring on a wiring board including a semiconductor package or another type of board.
2. Description of the Related Art
With the trend toward higher miniaturization and higher complexity of wiring patterns formed on wiring boards, there has developed a need for high-precision wiring forming techniques.
Further, the shrinking size and increasing performance of various kinds of components are driving the trend toward multilayer wiring boards. A multilayer wiring board is constructed by stacking a plurality of boards on top of another. In particular, a technique generally known as the buildup technique has come into common use in recent years; in this technique, a rigid layer containing glass cloth is formed as the center board of the multilayer board, on top of which thin insulating layers are stacked sequentially, with fine-featured wiring formed thereon, and again thin insulating layers are stacked in like manner, the process being repeated to complete the fabrication of the multilayer board.
In such multilayer boards, as vias interconnecting the wiring patterns on the respectively stacked layers are formed in addition to the wiring formed on the surface of each layer, particularly high precision is required in the formation of wiring for the multilayer board.
Generally, wiring is formed on a multilayer board by exposing the board based on design data defining a wiring pattern, and by developing it to print the desired pattern on the board and etching away unwanted portions.
FIG. 33 is a flowchart illustrating a prior art wiring forming process.
Usually, in the manufacturing process of a wiring board such as a semiconductor package, wiring for a plurality of packages or wiring boards is formed on a single large-sized board, and the large-sized board is then cut into individual unit packages or unit wiring boards.
First, in step S901, the circuit wiring for the unit wiring board is designed by CAD to generate circuit design data. That is, the circuit design data means data containing circuit design information for one unit. The wiring pattern to be formed on the wiring board is made up of conductive portions (generally called the lines) and regions (generally called the spaces) between the conductors.
Next, in step S902, considering etching line width in addition to job deck information describing how the circuit design data for each unit wiring board should be arranged on the large-sized wiring board, board layout design (an imposition job) is performed using CAM, to create board design data.
In step S903, a set of photomask is made based on the board design data created in step S902. More specifically, either the lines or the spaces are chosen as the portions to be exposed or not exposed on the board, and the portions not to be exposed are masked.
In step S904, a resist layer is exposed to light through the photomask. In this specification, the thus exposed board is called the “post-exposure board”.
Usually, in the board exposing process, a post-exposure board that exactly matches the board design data cannot always be obtained because physical and chemical parameters greatly affect the exposure process. FIG. 34 is a top plan view showing a distorted board as an example. Deformation such as distortion, shrinkage/expansion, etc. occurs in the board 200 itself because of the ambient temperature, the mechanical stress applied to the board, etc.
FIGS. 35 and 36 are diagrams schematically explaining the situation when exposure is performed on a distorted board: FIG. 35 shows the post-exposure board 201 which was exposed in an ideal condition free from distortion, and FIG. 36 shows the post-exposure board 202 which was exposed in a distorted condition.
When the distortion-free ideal board 201 shown in FIG. 35 is subjected to exposure faithfully to the board design data, the pattern 250 can be formed in each designated area. On the other hand, when the distorted board 202 is subjected to exposure faithfully to the board design data, the pattern 250 is not formed in the designate area but is displaced as shown in FIG. 36. Accordingly, when forming wiring on a wiring board, the shrinkage/expansion of the board must be considered in advance. In the conventional wiring forming process, the amount of displacement existing between the exposure pattern on the post-exposure board and the board design data is calculated, and data (called “a scaling correction value”) for correcting the board design data is created. This scaling correction value is fed back to the CAM process in step S902, to apply the scaling correction to the board design data. Then, the mask is remade using the corrected board design data, and the exposure is performed. By repeating this process several times, the design data is found that can accommodate the board shrinkage/expansion and distortion which can occur during the exposure process.
When the desired post-exposure board has successfully been obtained by exposing it using the design data created by considering the shrinkage/expansion and distortion of the board then, in step S905, this post-exposure board is developed, and unwanted portions of the resist layer are removed to form a resist pattern. In the case of a subtractive process, the resist pattern is left in the shape of the wiring pattern to be formed. In a semi-additive process, the resist pattern is formed in such a manner as to expose the underlying conductive layer in the shape of the wiring pattern to be formed.
Then, in step S906, the thus developed post-exposure board is etched. In this specification, the board subjected to etching is called the “post-etching board”. In the case of the subtractive process, the portions of the conductive layer which are exposed through the resist pattern are removed by etching, and then the resist pattern is removed to form the wiring. In the case of the semi-additive process, a metal that forms the wiring is deposited by plating (copper plating) onto the conductive layer portions exposed through the resist pattern, and a metallization pattern is formed to form the wiring on the conductive layer. Then, the resist pattern is removed, and the portions of the conductive layer which are exposed through the metallization pattern forming the wiring are etched away, thus completing the formation of the wiring.
The etching process, like the exposure process, is greatly affected by physical or chemical parameters, and the etching cannot always be accomplished faithfully to the board design data. For example, the etching may be displaced, or the etching lines may be formed too thick or too thin, compared with the board design data. In this specification, such errors relating to etching are called “etching errors”.
In the prior art, to eliminate etching errors, the amount of displacement existing between the etching pattern on the post-etching board and the board design data is calculated, and data (called the “etching correction value”) for correcting the board design data is created. This etching correction value is fed back to the CAM process in step S902, to apply the etching correction to the board design data. Then, the post-etching board is obtained through the steps S903 to S906 by using the thus corrected board design data. By repeating this process, the board design data that minimizes the etching error can be obtained. Then, using the thus obtained optimum board design data, a wiring board having a plurality of unit wiring boards each having the intended wiring formed thereon is mass-produced.
As described above, in the prior art wiring forming process, scaling correction is applied for the board distortion and shrinkage/expansion that can occur during the exposure process, and etching correction is applied for etching errors that occur during the etching process, thereby correcting the board design data as needed and finding the optimum board design data through trial and error, and the wiring board is mass-produced using the thus obtained board design data.
As described above, the prior art process is time consuming, because the series of scaling correction processes consisting of mask making, exposure, and post-exposure board test has to be repeated several times in order to obtain the board design data considering the board distortion and shrinkage/expansion that can occur during the exposure process. Furthermore, the prior art process is uneconomical and wasteful as the process involves producing unusable boards.
Further, while the correction is applied so as to generate the board design data that can accommodate the distortion and shrinkage/expansion of the board as explained with reference to FIGS. 34 to 36, this correction is unique to the trial board currently being produced, and is, so to speak, a “fixed” correction value. Accordingly, in the trial production of an entirely different new board, the previously used scaling correction may be useful to a certain extent to obtain a rough trend, but it is inefficient because an entirely new scaling correction has to be applied to a new board.
What has been said of the scaling correction above is also true of the etching correction for etching errors; that is, it is inefficient and uneconomical to determine, after etching is completely finished, whether the board design data used for the etching was really appropriate data or not.
Furthermore, the exposure using a photomask involves the cost of making the photomask not only in mass production of the board but also in trial production. In particular, if the completed board does not match the design data, the mask specifically made for the board by applying the scaling correction during the trial production is rendered defective and has to be discarded, which is uneconomical.
In the prior art wiring forming system, the board during the wiring forming process can be tested only after the exposure and after the etching, and cannot be tested, for example, after developing the post-exposure board; therefore, there is still room for improving the accuracy in wiring formation.
Moreover, in the prior art wiring forming system, in the case of a multilayer board, not only is it difficult to align the plurality of layers, but it is also difficult to grasp the wiring condition on each of the stacked layers and to form interconnections between the layers. This poses a problem in the future when further miniaturization of wiring is expected.
In view of the above-outlined problems, it is an object of the present invention to provide a high-precision wiring forming system that can perform the design, testing, and formation of wiring easily and at high speed, can reduce the cost involved in the wiring formation and wiring design, can accommodate further miniaturization of wiring, and can flexibly cope with design changes.